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19-2201; Rev 2; 11/02
1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
General Description
The MAX9320/MAX9320A are low-skew, 1-to-2 differential drivers designed for clock and data distribution. The input is reproduced at two differential outputs. The differential input can be adapted to accept single-ended inputs by applying an external reference voltage. The MAX9320/MAX9320A feature ultra-low propagation delay (208ps), part-to-part skew (20ps), and output-tooutput skew (6ps) with 30mA maximum supply current, making these devices ideal for clock distribution. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.25V to +3.8V supply range, allowing high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.25V to -3.8V supply. The pinout is the only difference between the MAX9320 and MAX9320A. Multiple pinouts are provided to simplify routing across a backplane to either side of a doublesided board. These devices are offered in space-saving 8-pin SOT23, MAX, and SO packages.
Features
o Improved Second Source of the MC10LVEP11 (MAX9320) o +2.25V to +3.8V Differential HSTL/LVPECL Operation o -2.25V to -3.8V LVECL Operation o Low 22mA (typ) Supply Current o 20ps (typ) Part-to-Part Skew o 6ps (typ) Output-to-Output Skew o 208ps (typ) Propagation Delay o Minimum 300mV Output at 3GHz o Outputs Low for Open Input o ESD Protection >2kV (Human Body Model) o Available in Thermally Enhanced Exposed-Pad SO Package
MAX9320/MAX9320A
Applications
Precision Clock Distribution Low-Jitter Data Repeater Protection Switching
PART MAX9320EKA-T MAX9320ESA MAX9320EUA* MAX9320AEKA-T
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 8 SOT23-8 8 SO-EP** 8 MAX 8 SOT23-8 TOP MARK AALJ -- -- AAIW
*Future product--Contact factory for availability. **EP = Exposed pad.
Pin Configurations
Q0 1 Q0 2 100k Q1 3 100k Q1 4 5 VEE D4 VEE 6D D3 100k 100k 5 Q1 D4 VEE 6 Q1 D3 100k 100k 5 Q1 6 Q1 8 VCC 60k 7D VEE 2 VCC 1 VCC 60k 7 Q0 VEE 2 60k 8 Q0 VCC 1 8 Q0 7 Q0
MAX9320
MAX9320A
MAX9320
VCC
MAX/SO
SOT23
SOT23
________________________________________________________________ Maxim Integrated Products
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1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9320/MAX9320A
ABSOLUTE MAXIMUM RATINGS
VCC to VEE ..........................................................................+4.1V D or D .................................................. VEE - 0.3V to VCC + 0.3V D to D .................................................................................3.0V Continuous Output Current .................................................50mA Surge Output Current........................................................100mA Junction-to-Ambient Thermal Resistance in Still Air 8-Pin SOT23.............................................................+112C/W 8-Pin MAX ..............................................................+221C/W 8-Pin SO...................................................................+170C/W Junction-to-Ambient Thermal Resistance with 500 LFPM Airflow 8-Pin SOT23...............................................................+78C/W 8-Pin MAX ..............................................................+155C/W 8-Pin SO.....................................................................+99C/W Junction-to-Case Thermal Resistance 8-Pin SOT23...............................................................+80C/W 8-Pin MAX ................................................................+39C/W 8-Pin SO.....................................................................+40C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (D, D, Q_, Q_) .................................>2kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50 1% to VCC - 2V. Typical values are at VCC - VEE = +3.3V, VIHD = VCC 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER SYMBOL CONDITIONS -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
DIFFERENTIAL INPUT (D, D) High Voltage of Differential Input Low Voltage of Differential Input VIHD VEE + 1.2 VCC VEE + 1.2 VCC VEE + 1.2 VCC V
VILD For VCC - VEE < +3.0V For VCC - VEE +3.0V
VEE
VCC - 0.1 VCC - VEE 3.0 150
VEE
VCC - 0.1 VCC - VEE 3.0 150
VEE
VCC - 0.1 VCC - VEE 3.0 150
V
0.1 0.1
0.1 0.1
0.1 0.1
Differential Input Voltage
VIHD - VILD
V
Input High Current D Input Low Current D Input Low Current Single-Ended Output High Voltage
IIH IILD IILD -10 -150
A A A
100 +150
-10 -150
100 +150
-10 -150
100 +150
DIFFERENTIAL OUTPUTS (Q_, Q_) VOH Figure 1 VCC - 1.135 VCC - 0.885 VCC - 1.07 VCC - 0.82 VCC - 1.01 VCC - 0.76 V
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1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50 1% to VCC - 2V. Typical values are at VCC - VEE = +3.3V, VIHD = VCC 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, 3)
PARAMETER Single-Ended Output Low Voltage Differential Output Voltage POWER SUPPLY Supply Current IEE (Note 4) 20 28 22 28 23 30 mA SYMBOL CONDITIONS -40C MIN VCC - 1.935 550 TYP MAX MIN +25C TYP MAX VCC - 1.62 MIN VCC - 1.81 550 +85C TYP MAX VCC - 1.56 UNITS
MAX9320/MAX9320A
VOL VOH - VOL
Figure 1
VCC VCC - 1.685 - 1.87 550
V
Figure 1
mV
AC ELECTRICAL CHARACTERISTICS
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50 1% to VCC - 2V, input frequency = 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to the smaller of 3V or VCC - VEE. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Note 5)
PARAMETER Differential Input-toOutput Delay Output-toOutput Skew Part-to-Part Skew Added Random Jitter (Note 8) Added Deterministic Jitter SYMBOL tPLHD, tPHLD tSKOO tSKPP CONDITIONS -40C MIN 145 TYP 220 MAX 265 MIN 155 +25C TYP 208 MAX 265 MIN 160 +85C TYP 203 MAX 270 UNITS
Figure 1
ps
(Note 6) (Note 7) fIN = 1.5GHz, clock pattern
6 20 1.7 0.6
30 120 2.8 1.5
6 20 1.7 0.6
30 110 2.8 1.5
6 20 1.7 0.6
30 110 2.8
ps ps
tRJ
fIN = 3.0GHz, clock pattern 3.0Gbps 223-1 PRBS pattern (Note 8)
ps (RMS) 1.5 ps (p-p)
tDJ
57
80
57
80
57
80
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1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9320/MAX9320A
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC - VEE = +2.25V to +3.8V, outputs loaded with 50 1% to VCC - 2V, input frequency = 1.5GHz, input transition time = 125ps (20% to 80%), VIHD = VEE + 1.2V to VCC, VILD = VEE to VCC - 0.15V, VIHD - VILD = 0.15V to the smaller of 3V or VCC - VEE. Typical values are at VCC - VEE = +3.3V, VIHD = VCC - 1V, VILD = VCC - 1.5V, unless otherwise noted.) (Note 5)
PARAMETER SYMBOL CONDITIONS VOH - VOL 300mV, clock pattern, Figure 1 fMAX VOH - VOL 550mV, clock pattern, Figure 1 -40C MIN 3.0 TYP MAX MIN 3.0 +25C TYP MAX MIN 3.0 GHz 2.0 2.0 2.0 +85C TYP MAX UNITS
Switching Frequency
Output Rise/Fall Time (20% to 80%)
tR, tF
Figure 1
50
88
120
50
89
120
50
90
120
ps
Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters production tested at TA = +25C. Guaranteed by design and characterization over the full operating temperature range. Note 4: All pins open except VCC and VEE. Note 5: Guaranteed by design and characterization. Limits are set at 6 sigma. Note 6: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Note 7: Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. Note 8: Device jitter added to the input signal.
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1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
Typical Operating Characteristics
(VCC = +3.3V, VEE = 0, input transition time = 125ps (20% to 80%), VIHD = VCC - 1V, VILD = VCC - 1.5V, fIN = 1.5GHz, outputs loaded with 50 to VCC - 2V, TA = +25C, unless otherwise noted.)
OUTPUT AMPLITUDE, VOH - VOL vs. FREQUENCY
0.8 OUTPUT AMPLITUDE (V) 0.7 0.6 0.5 0.4 0.3 0.2 86 0.1 0 -40 -15 10 35 60 85 0 500 1000 1500 2000 2500 3000 3500 FREQUENCY (MHz) TEMPERATURE (C) 85 -40 -15 10 35 60 85 TEMPERATURE (C)
MAX9320 toc02
MAX9320/MAX9320A
SUPPLY CURRENT, IEE vs. TEMPERATURE
24 23 SUPPLY CURRENT (mA) 22 21 20 19 18 17 16 15
MAX9320 toc01
TRANSITION TIME vs. TEMPERATURE
MAX9320 toc03
25
0.9
91 90 TRANSITION TIME (ps) 89 88 tR 87
tF
PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT, VIHD
VIHD - VILD = 0.5V 220 PROPAGATION DELAY (ps) 215 210 205 tPHLD 200 195 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8 VIHD (V)
MAX9320 toc04
PROPAGATION DELAY vs. TEMPERATURE
230 PROPAGATION DELAY (ps) 220 210 200 190 180 170 160 -40 -15 10 35 60 85 TEMPERATURE (C) tPHLD tPLHD
MAX9320 toc05
225
240
tPLHD
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1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9320/MAX9320A
Pin Description (MAX9320)
PIN MAX/SO 1 2 3 4 5 6 7 8 SOT23 8 7 6 5 2 4 3 1 NAME Q0 Q0 Q1 Q1 VEE D D VCC FUNCTION Noninverting Q0 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q0 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q1 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q1 Output. Typically terminate with 50 resistor to VCC - 2V. Negative Supply Voltage Inverting Differential Input. 60k pullup to VCC and 100k pulldown to VEE. Noninverting Differential Input. 100k pulldown to VEE. Positive Supply Voltage. Bypass from VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device.
Pin Description (MAX9320A)
PIN SOT23 1 2 3 4 5 6 7 8 NAME FUNCTION Positive Supply Voltage. Bypass from VCC to VEE with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. Negative Supply Voltage Inverting Differential Input. 60k pullup to VCC and 100k pulldown to VEE. Noninverting Differential Input. 100k pulldown to VEE. Inverting Q1 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q1 Output. Typically terminate with 50 resistor to VCC - 2V. Inverting Q0 Output. Typically terminate with 50 resistor to VCC - 2V. Noninverting Q0 Output. Typically terminate with 50 resistor to VCC - 2V.
VCC VEE D D Q1 Q1 Q0 Q0
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1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
D VIHD -VILD D tPLHD Q_ VOH -VOL Q VOL tPHLD VOH VILD VIHD
A single-ended input of 100mV around a reference voltage or a differential input of at least 100mV switches the outputs to the VOH and VOL levels specified in the DC Electrical Characteristics table.
MAX9320/MAX9320A
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount ceramic 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the 0.01F value capacitor closest to the device. Use multiple parallel vias for low inductance.
80% 0 (DIFFERENTIAL) (Q_) - (Q_) 20% tR
80% 0 (DIFFERENTIAL) 20% tF
Traces
Input and output trace characteristics affect the performance of the MAX9320/MAX9320A. Connect each signal of a differential input or output to a 50 characteristic impedance trace. Minimize the number of vias to prevent impedance discontinuities. Reduce reflections by maintaining the 50 characteristic impedance through connectors and across cables. Reduce skew within a differential pair by matching the electrical length of the traces. The exposed-pad (EP) SO package can be soldered to the PC board for enhanced thermal performance. If the EP is not soldered to the PC board, the thermal resistance is the same as the regular SO package. The EP is connected to the chip VEE supply. Be sure that the pad does not touch signal lines or other supplies. Contact the Maxim Packaging department for guidelines on the use of EP packages.
Figure 1. Differential Transition Time and Propagation Delay Timing Diagram
Detailed Description
The MAX9320/MAX9320A low-skew, 1-to-2 differential drivers are designed for clock and data distribution. For interfacing to differential HSTL and LVPECL signals, these devices operate over a +2.25V to +3.8V supply range, allowing high-performance clock and data distribution in systems with a nominal +2.5V or +3.3V supply. For differential LVECL operation, these devices operate from a -2.25V to -3.8V supply.
Inputs
The maximum magnitude of the differential input from D to D is VCC - VEE or 3.0V, whichever is less. This limit also applies to the difference between any reference voltage input and a single-ended input. The differential inputs have bias resistors that drive the outputs to a differential low when the inputs are open. The inverting input, D, is biased with a 60k pullup to VCC and a 100k pulldown to VEE. The noninverting input, D, is biased with a 100k pulldown to VEE. Specifications for the high and low voltages of the differential input (VIHD and VILD) and the differential input voltage (VIHD - VILD) apply simultaneously (VILD cannot be higher than VIHD).
Output Termination
Terminate outputs through 50 to VCC - 2V or use an equivalent Thevenin termination. Terminate both outputs and use the same termination on each for the lowest output-to-output skew. When a single-ended signal is taken from a differential output, terminate both outputs. For example, if Q0 is used as a single-ended output, terminate both Q0 and Q0.
Chip Information
TRANSISTOR COUNT: 182
Outputs
Output levels are referenced to VCC and are considered LVPECL or LVECL, depending on the level of the VCC supply. With VCC connected to a positive supply and VEE connected to GND, the outputs are LVPECL. The outputs are LVECL when VCC is connected to GND and VEE is connected to a negative supply.
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1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers MAX9320/MAX9320A
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SOT23, 8L.EPS
8
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1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
8L, SOIC EXP. PAD.EPS
MAX9320/MAX9320A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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